The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2025
Filed:
Oct. 30, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Joshua Stacey, Chandler, AZ (US);
Whitney Bryks, Tempe, AZ (US);
Sarah Blythe, Chandler, AZ (US);
Peumie Abeyratne Kuragama, Chandler, AZ (US);
Junxin Wang, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/18 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/295 (2013.01); H01L 23/18 (2013.01); H01L 23/31 (2013.01); H01L 23/5226 (2013.01);
Abstract
An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.