The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Feb. 05, 2024
Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventors:

Gabriel R. Cueva, Bedford, NH (US);

Timothy E. Boles, Tyngsboro, MA (US);

Wayne Mack Struble, Franklin, MA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/74 (2006.01); H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 21/8252 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 23/66 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0254 (2013.01); H01L 21/02381 (2013.01); H01L 21/743 (2013.01); H01L 21/746 (2013.01); H01L 21/7605 (2013.01); H01L 21/76202 (2013.01); H01L 21/76205 (2013.01); H01L 21/76224 (2013.01); H01L 21/8252 (2013.01); H01L 23/5286 (2013.01); H01L 23/535 (2013.01); H01L 23/66 (2013.01); H01L 27/0605 (2013.01); H01L 29/0649 (2013.01); H01L 29/2003 (2013.01);
Abstract

Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. An example method for making a semiconductor structure includes forming a trench in an interconnect area of a substrate between first and second device areas in the semiconductor structure, forming a low dielectric constant material region in the trench, forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench, forming a first device in the III-nitride material layer in the first device area, forming a second device in the III-nitride material layer in the second device area, and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.


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