The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Oct. 06, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Anurag Jindal, Austin, TX (US);

Kapil Narula, Austin, TX (US);

Rahul Kalyan, Austin, TX (US);

Hongkun Liang, Beijing, CN;

Assignee:

NXP USA, Inc., Austin, TX (US);

Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01);
Abstract

Test coverage for a circuit design may be determined by obtaining node testability data and physical location data for each node of a plurality of nodes in the circuit design. A determination is made that one or more low test coverage areas within the circuit design include untested nodes based on the node testability data and the physical location data of each node of the plurality of nodes. Test coverage data is generated for the circuit design including at least an identification of the one or more low test coverage areas.


Find Patent Forward Citations

Jindal, Anurag. (2025). Identifying test coverage gaps for integrated circuit designs based on node testability and physical design data (U.S. Patent No. 12265776). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12265776

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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