The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2025
Filed:
Jul. 31, 2023
Applicant:
Synopsys, Inc., Sunnyvale, CA (US);
Inventors:
Amyn A. Poonawala, Santa Clara, CA (US);
Jason Jiale Shu, San Jose, CA (US);
Thomas Chrisptopher Cecil, Menlo Park, CA (US);
Assignee:
Synopsys, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 20/10 (2019.01); G03F 1/36 (2012.01); G03F 1/70 (2012.01); G03F 1/76 (2012.01); G06F 30/33 (2020.01); G06F 30/39 (2020.01); G06N 3/08 (2023.01);
U.S. Cl.
CPC ...
G03F 1/70 (2013.01); G03F 1/36 (2013.01); G03F 1/76 (2013.01); G06F 30/33 (2020.01); G06F 30/39 (2020.01); G06N 3/08 (2013.01);
Abstract
Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. These techniques include providing, by a processor, a design pattern for a semiconductor device as input to a trained machine learning (ML) model. The techniques further include performing, using the ML Model, a plurality of dilated convolutions relating to the design pattern, and inferring, using the ML model, one or more masks for use in manufacturing the semiconductor device, based on the plurality of dilated convolutions.