The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2025
Filed:
Sep. 29, 2024
Nanjing University of Posts and Telecommunications, Jiangsu, CN;
Nantong Institute of Nanjing University of Posts and Telecommunications Co., Ltd, Jiangsu, CN;
Zhikuang Cai, Jiangsu, CN;
Xiaoting Liu, Jiangsu, CN;
Luping Zhang, Jiangsu, CN;
Zixuan Wang, Jiangsu, CN;
Dapeng Yan, Jiangsu, CN;
Binbin Xu, Jiangsu, CN;
Haiyan Sun, Jiangsu, CN;
Lu Liu, Jiangsu, CN;
Yufeng Guo, Jiangsu, CN;
Abstract
A universal test chiplet for testing a plurality of chiplets to be tested is provided. The universal test chiplet includes a chiplet test control circuit module, a test data distribution circuit module, a memory test configuration circuit module, and a chiplet test interface circuit module. The chiplet test control circuit module is configured to provide test data and configure test modes for the chiplets to be tested. The test data distribution circuit module is configured to distribute the test data required by each of the chiplets to be tested from a test data bus. The memory test configuration circuit module is configured to provide test circuits for memories of the chiplets to be tested and automatically generate a test vector. The chiplet test interface circuit module is configured to transmit the test data to the chiplets to be tested in any direction through chiplet test interfaces.