The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Dec. 12, 2024
Applicant:

Diodes Incorporated, Plano, TX (US);

Inventors:

Ching-Wen Wang, New Taipei, TW;

Jie Li, New Taipei, TW;

Ming-Wei Tsai, New Taipei, TW;

Chiao-Shun Chuang, New Taipei, TW;

Assignee:

Diodes Incorporated, Plano, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 21/04 (2006.01); H10D 62/832 (2025.01);
U.S. Cl.
CPC ...
H10D 62/107 (2025.01); H01L 21/046 (2013.01); H10D 62/8325 (2025.01);
Abstract

A method of manufacturing a semiconductor structure is provided. A substrate including a first silicon carbide layer and a second silicon carbide layer under the first silicon carbide layer is formed. The substrate includes a unit region and a termination region surrounding the unit region. A first guard ring structure is formed in the termination region and the first silicon carbide layer, adjoining a top surface of the first silicon carbide layer. A second guard ring structure is formed in the termination region and the second silicon carbide layer. Second guard ring well regions of the second guard ring structure correspond one-on-one to first guard ring well regions of the first guard ring structure. Each of the second guard ring well regions overlaps with a corresponding one of the first guard ring well regions in a vertical direction perpendicular to the top surface of the substrate.


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