The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2025
Filed:
Sep. 24, 2021
Intel Corporation, Santa Clara, CA (US);
Itamar Levin, Holon, IL;
Tali Warshavsky, Ramat Gan, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
An Automatic Gain Control (AGC) SERDES circuit may be used to provide improved gain control for SERDES operation. This AGC SERDES circuit uses an initial gain convergence to determine and store an initial gain level. Once the initial gain convergence is complete, the AGC SERDES circuit uses a signal peak tracking to reduce or prevent saturation events. By setting the gain target based on tracked changes in the equalizer coefficients, the AGC SERDES circuit adapts the gain target to reduce or prevent saturation events and provide the improved communication throughput. A SERDES receiver circuit also provides improved performance using an improved convergence flow within its subcomponent blocks. The improved convergence flow also provides the ability to track environmental changes, voltage changes, and changes to input parameters, and can be performed while data is running on the link to provide continuously improved communication channel performance.