The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Nov. 02, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Neil Quinn Murray, Hsinchu, TW;

Katherine H. Chiang, New Taipei, TW;

Chung-Te Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78642 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 27/1255 (2013.01);
Abstract

The present disclosure relates to a method of manufacturing a semiconductor structure. The method may be performed by forming a first source/drain region. A first dielectric layer is formed above the first source/drain region. A portion of the first dielectric layer is removed. A channel region is formed along a sidewall of the first dielectric layer. A gate region is formed along a sidewall of the channel region. A second dielectric layer is formed above the first dielectric layer and the gate region. A portion of the second dielectric layer is removed to form an opening that exposes the channel region. A second source/drain region is formed within the opening.


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