The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Jan. 18, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Meng-Han Lin, Hsinchu, TW;

Te-An Chen, Taichung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 29/0649 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method for forming an integrated circuit includes following operations. A substrate is received. The substrate includes a first region, a second region and an isolation structure. The isolation structure has a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed on a portion of the first top surface, a top of the second top surface and the boundary. A dielectric structures is formed over the substrate. Top surfaces of the dielectric structure, the first device, the second device and the dummy structure are aligned with each other. A first metal gate is formed in the first device, and a second metal gate is formed in the second device.


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