The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Apr. 04, 2024
Applicant:

Diodes Incorporated, Plano, TX (US);

Inventors:

Jie Li, New Taipei, TW;

Ming-Wei Tsai, New Taipei, TW;

Chiao-Shun Chuang, New Taipei, TW;

Ching-Wen Wang, New Taipei, TW;

Assignee:

Diodes Incorporated, Plano, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/04 (2006.01); H10D 12/01 (2025.01); H10D 62/832 (2025.01);
U.S. Cl.
CPC ...
H01L 21/0465 (2013.01); H10D 12/031 (2025.01); H10D 62/8325 (2025.01);
Abstract

Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask and epitaxial layer on a semiconductor substrate, and forming a first doped region in the epitaxial layer by performing a first implantation through the first patterned hard mask. A second doped region is formed in the epitaxial layer by performing a second implantation through the first patterned hard mask, with the first doped region at least partially overlapping the second doped region. A second patterned hard mask is formed, which surrounds the first patterned hard mask and covers at least a portion of the first doped region. A third doped region is formed in the epitaxial layer by performing a third implantation through the first patterned hard mask and the second patterned hard mask.


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