The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Feb. 22, 2023
Applicant:

Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;

Inventors:

Zhenan Lai, Shanghai, CN;

Junsheng Chen, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G11C 11/419 (2013.01); G11C 2029/1204 (2013.01);
Abstract

The present application discloses a design for testability circuit of an SRAM. In a write path circuit detection mode of a fault diagnosis logic control module, a write path circuit is in an on state, a write data bit multiplexer is in a selected state, a read data bit multiplexer is in a deselected state, a read path circuit is in an on state, and a memory cell is in a selected state; in a read path circuit detection mode, the write path circuit is in an off state, the write data bit multiplexer is in a selected state, the read data bit multiplexer is in a deselected state, the read path circuit is in an on state, and the memory cell is in a deselected state. A bit line signal end is connected to a test signal outputted by a signal generation circuit.


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