The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Dec. 10, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert Valentine, Kiryat Tivon, IL;

Dan Baum, Haifa, IL;

Zeev Sperber, Zichron Yaakov, IL;

Jesus Corbal, Barcelona, ES;

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Bret L. Toll, Hillsboro, OR (US);

Mark J. Charney, Lexington, MA (US);

Barukh Ziv, Haifa, IL;

Alexander Heinecke, San Jose, CA (US);

Milind Girkar, Sunnyvale, CA (US);

Simon Rubanovich, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/485 (2006.01); G06F 7/487 (2006.01); G06F 7/76 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 7/485 (2013.01); G06F 7/4876 (2013.01); G06F 7/762 (2013.01); G06F 9/3001 (2013.01); G06F 9/30032 (2013.01); G06F 9/30038 (2023.08); G06F 9/30043 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/30134 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/30185 (2013.01); G06F 9/30196 (2013.01); G06F 9/3818 (2013.01); G06F 9/3836 (2013.01); G06F 17/16 (2013.01); G06F 2212/454 (2013.01);
Abstract

Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.


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