The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2025
Filed:
Feb. 02, 2022
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/8234 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 21/30604 (2013.01); H01L 21/308 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 27/0688 (2013.01); H01L 27/0886 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01);
Abstract
Methods of forming a plurality of transistor stacks are provided. A method of forming a plurality of transistor stacks includes etching a plurality of nanosheets, using a plurality of spacers that are on sidewalls of a plurality of semiconductor fins as an etch mask, to provide a plurality of spaced-apart nanosheet stacks that each have at least one of the semiconductor fins thereon.