The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Nov. 21, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tsai-Hao Hung, Hsinchu, TW;

Ping-Cheng Ko, Hsinchu, TW;

Tzu-Yang Lin, Hsinchu, TW;

Fang-Yu Liu, Hsinchu, TW;

Cheng-Han Wu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/687 (2006.01); H01L 21/66 (2006.01); H01L 21/67 (2006.01); H01L 21/677 (2006.01); H05F 1/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/68757 (2013.01); H01L 21/67167 (2013.01); H01L 21/67173 (2013.01); H01L 21/6719 (2013.01); H01L 21/67196 (2013.01); H01L 21/67201 (2013.01); H01L 21/67242 (2013.01); H01L 21/67742 (2013.01); H01L 22/10 (2013.01); H05F 1/00 (2013.01);
Abstract

Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.


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