The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Sep. 29, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Jianyong Qin, Hefei, CN;

Jianni Li, Hefei, CN;

Zhonglai Liu, Hefei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/46 (2006.01); G06F 1/04 (2006.01); G06F 13/16 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/46 (2013.01); G06F 1/04 (2013.01); G06F 13/1689 (2013.01); G11C 29/12005 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01);
Abstract

A test circuit includes first integration circuit configured to receive first test signal and integrate first test signal to output first integrated signal; second integration circuit configured to receive second test signal and integrate second test signal to output second integrated signal, where first test signal and second test signal are signals inverted with respect to each other, value of first integrated signal is product of duty cycle of first test signal and a voltage amplitude of power supply, and value of second integrated signal is product of duty cycle of second test signal and voltage amplitude of power supply; and comparison circuit connected to first and second integration circuits. The comparison circuit is configured to output high-level signal in response to first integrated signal being greater than second integrated signal, and output low-level signal in response to second integrated signal being greater than first integrated signal.


Find Patent Forward Citations

Qin, Jianyong. (2025). Test circuit, test method and memory (U.S. Patent No. 12254941). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12254941

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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