The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Mar. 15, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Varghese George, Folsom, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Aravindh Anantaraman, Folsom, CA (US);

Subramaniam Maiyuran, Gold River, CA (US);

SungYe Kim, Folsom, CA (US);

Valentin Andrei, San Jose, CA (US);

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Joydeep Ray, Folsom, CA (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Nicolas C. Galoppo von Borries, Portland, OR (US);

Prasoonkumar Surti, Folsom, CA (US);

Mike Macpherson, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06F 16/17 (2019.01); G06N 20/00 (2019.01); G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 16/1724 (2019.01); G06N 20/00 (2019.01); G06T 1/60 (2013.01);
Abstract

Apparatuses including general-purpose graphics processing units having on chip dense memory for temporal buffering are disclosed. In one embodiment, a graphics multiprocessor includes a plurality of compute engines to perform first computations to generate a first set of data, cache for storing data, and a high density memory that is integrated on chip with the plurality of compute engines and the cache. The high density memory to receive the first set of data, to temporarily store the first set of data, and to provide the first set of data to the cache during a first time period that is prior to a second time period when the plurality of compute engines will use the first set of data for second computations.


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