The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Jan. 27, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Deepak Dasalukunte, Beaverton, OR (US);

Richard Dorrance, Hillsboro, OR (US);

Hechen Wang, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/065 (2023.01); G06N 3/047 (2023.01); H04L 45/586 (2022.01); H04L 49/109 (2022.01);
U.S. Cl.
CPC ...
G06N 3/065 (2023.01); G06N 3/047 (2023.01); H04L 45/586 (2013.01); H04L 49/109 (2013.01);
Abstract

Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of supertiles. An analog-to-digital converter (ADC) of the analog router may convert the first analog output to a first digital output and transmit the first digital output to the second supertile via a communications bus of the NoC.


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