The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2025
Filed:
Jun. 10, 2022
Applicant:
Synopsys, Inc., Sunnyvale, CA (US);
Inventors:
Joydeep Banerjee, Karnataka, IN;
Mayur Bubna, Karnataka, IN;
Debabrata Das Roy, Karnataka, IN;
Solaiman Rahim, San Francisco, CA (US);
Assignee:
SYNOPSYS, INC., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3315 (2020.01); G06F 30/3312 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3315 (2020.01); G06F 30/3312 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01);
Abstract
A method includes: receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type; identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector, and determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.