The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Dec. 12, 2023
Applicant:

Lodestar Licensing Group, Llc., Evanston, IL (US);

Inventors:

Brent Keeth, Boise, ID (US);

Owen Fay, Meridian, ID (US);

Chan H. Yoo, Boise, ID (US);

Roy E. Greeff, Boise, ID (US);

Matthew B. Leslie, Boise, ID (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G11C 11/4093 (2006.01); G11C 29/12 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
G06F 12/0653 (2013.01); G06F 12/0215 (2013.01); G11C 11/4093 (2013.01); G11C 29/12 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); G06F 2212/1016 (2013.01); G11C 2211/4062 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01);
Abstract

Apparatus and methods are described, including memory devices and systems. Memory devices, systems and methods may include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some cases, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods may include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.


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