The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2025

Filed:

Aug. 23, 2023
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Shafquat Jahan Ahmed, Greater Noida, IN;

Dhori Kedar Janardan, Ghaziabad, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H10B 10/18 (2023.02);
Abstract

A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.


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Ahmed, Shafquat. (2025). Sram cell layout including arrangement of multiple active regions and multiple gate regions (U.S. Patent No. 12250804). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12250804

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