The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2025
Filed:
Apr. 06, 2023
Nxp Usa, Inc., Austin, TX (US);
Divya Tripathi, Noida, IN;
Sadique Mohammad Iqbal, Karimganj, IN;
Anubhav Srivastava, Gorakhpur, IN;
Krishna Thakur, GautamBudh Nagar, IN;
Pragya Priya Malakar, Chandler, AZ (US);
John Pigott, Phoenix, AZ (US);
NXP USA, Inc., Austin, TX (US);
Abstract
A self-biased, closed loop, low current free running oscillator clock generator method and apparatus are provided with a current mode comparator connected to a trimming resistor and configured to compare an internally generated voltage reference Vsignal to a voltage feedback signal V, where the current mode comparator comprises a common gate amplifier connected to a current mirror circuit in a negative self-biased closed loop to generate a control current signal for controlling a current controlled oscillator to produce an output clock signal having a clock frequency based on the control current signal, where a frequency-to-voltage converter is connected in a feedback path to receive the output clock signal and is configured to produce the voltage feedback signal Vfor input to the current mode comparator, wherein the clock frequency of the output clock signal is tuned to a nominal locked output frequency fby the trimming resistor.