The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2025

Filed:

Apr. 25, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Yun-Feng Kao, New Taipei, TW;

Katherine H. Chiang, New Taipei, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/822 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); G11C 11/40 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/8221 (2013.01); H01L 23/528 (2013.01); G11C 11/40 (2013.01); H01L 23/5226 (2013.01);
Abstract

A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first transistor, and a second transistor. The interconnection structure includes a first metal line layer, a second metal line layer and a third metal line layer arranged over one another. The first transistor includes a gate structure. The second transistor is disposed adjacent to the first transistor, and includes a source/drain structure. The gate structure of the first transistor is disposed over and electrically connected to the first metal line layer, and the source/drain structure of the second transistor is arranged below and electrically connected to the second metal line layer through the third metal line layer. A manufacturing method of a semiconductor structure is also provided.


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