The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2025
Filed:
May. 12, 2022
Infineon Technologies Ag, Neubiberg, DE;
Bernhard Goller, Villach, AT;
Alexander Christian Binter, Villach, AT;
Tobias Hoechbauer, Villach, AT;
Martin Huber, Villach, AT;
Iris Moder, Villach, AT;
Matteo Piccin, Villach, AT;
Francisco Javier Santos Rodriguez, St Jakob im Rosental, AT;
Hans-Joachim Schulze, Taufkirchen, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
pa The method of processing a semiconductor wafer includes forming one or more epitaxial layers over its first main surface. It also involves forming one or more porous layers within the semiconductor wafer or within the epitaxial layers. Together, the semiconductor wafer, the epitaxial layer(s), and the porous layer(s) form a substrate. Next, doped regions of a semiconductor device are formed within the epitaxial layer(s). After forming these doped regions, a non-porous part of the semiconductor wafer is separated from the rest of the substrate along the porous layer(s).