The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Oct. 24, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Harry-Hak-Lay Chuang, Hsinchu County, TW;

Wu-Chang Tsai, Hsinchu, TW;

Tien-Wei Chiang, Taipei, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 61/00 (2023.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01);
U.S. Cl.
CPC ...
H10B 61/00 (2023.02); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H10N 50/01 (2023.02); H10N 50/10 (2023.02);
Abstract

A semiconductor device includes a bottom electrode via, a top electrode via over the bottom electrode via, a memory cell between the bottom electrode via and the top electrode via, a first dielectric layer over the memory cell, and a second dielectric layer over the first dielectric layer, and a via structure separated from the memory cell. A height of the via structure is substantially equal to a sum of a height of the bottom electrode via, a height of the memory cell, and a height of the top electrode via. The first dielectric layer partially surrounds a first portion of the via structure, and the second dielectric layer partially surrounds a second portion of the via structure. A height of the second portion of the via structure is greater than a height of the first portion of the via structure.


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