The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Apr. 01, 2022
Applicants:

Stmicroelectronics France, Montrouge, FR;

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Matthieu Nongaillard, Grenoble, FR;

Thomas Oheix, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 27/12 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/872 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 27/12 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/872 (2013.01);
Abstract

The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.


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