The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2025
Filed:
Apr. 12, 2024
Google Llc, Mountain View, CA (US);
Madhusudan K. Iyengar, Foster City, CA (US);
Christopher Malone, Mountain View, CA (US);
Woon-Seong Kwon, Santa Clara, CA (US);
Emad Samadiani, Cupertino, CA (US);
Melanie Beauchemin, Mountain View, CA (US);
Padam Jain, San Jose, CA (US);
Teckgyu Kang, Saratoga, CA (US);
Yuan Li, Sunnyvale, CA (US);
Connor Burgess, Alameda, CA (US);
Norman Paul Jouppi, Palo Alto, CA (US);
Nicholas Stevens-Yu, Palo Alto, CA (US);
Yingying Wang, Sunnyvale, CA (US);
Google LLC, Mountain View, CA (US);
Abstract
A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material ('TIM') having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.