The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Apr. 10, 2023
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventor:

Weijun Wan, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01);
Abstract

In certain aspects, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. At least one of the memory cells is set to one of 2levels corresponding to a piece of N-bits data, where Nis an integer greater than 1. The peripheral circuit is configured to apply a first program voltage to a select row of the memory cells, perform a first verification of the select row of the memory cells at a last level of the 2levels after applying the first program voltage, perform a first verify fail count (VFC) based on a result of the first verification and a first VFC criterion, apply a second program voltage greater than the first program voltage to the select row of the memory cells after performing the first VFC, and perform a second VFC based on the result of the first verification and a second VFC criterion different from the first VFC criterion within a period of applying the second program voltage.


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