The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2025
Filed:
Feb. 14, 2023
Synopsys, Inc., Mountain View, CA (US);
M Sultan M Siddiqui, Noida, IN;
Md Amir Arif, New Delhi, IN;
Tejaswini Saini, Uttam Nagar, IN;
Sudhir Kumar, Shastri Nagar, IN;
Ravindra Shrivastava, Noida, IN;
Synopsys, Inc., Sunnyvale, CA (US);
Abstract
An example described herein is a circuit including a dynamic complementary metal-oxide-semiconductor (CMOS) inverter level translator circuit and a capacitor. The dynamic CMOS inverter level translator circuit is electrically connected to a first power domain and has a first input node configured to receive a first trigger signal generated in the first power domain. The dynamic CMOS inverter level translator circuit has a second input node configured to receive a second trigger signal generated in a second power domain different from the first power domain. The capacitor is electrically coupled to an output node of the dynamic CMOS inverter level translator circuit. The capacitor selectively charges to the first power domain through the dynamic CMOS inverter level translator circuit based on the first trigger signal. The capacitor selectively discharges to provide a negative coupling voltage to a write assist supply node.