The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2025
Filed:
Apr. 29, 2022
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Pavan Kumar Reddy Aella, Eagle, ID (US);
Kolya Yastrebenetsky, Boise, ID (US);
Masuji Honjo, Boise, ID (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/20 (2023.01); G11C 13/00 (2006.01); H10B 63/10 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10N 70/231 (2023.02); G11C 13/0004 (2013.01); H10B 63/10 (2023.02); H10N 70/061 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/882 (2023.02); G11C 2213/52 (2013.01); H10N 70/883 (2023.02); H10N 70/884 (2023.02);
Abstract
A memory cell can include a top lamina layer, a bottom lamina layer, and a phase change material (PCM) layer between the top lamina layer and the bottom lamina layer. The PCM layer can have a top surface in direct contact with the top lamina layer and a bottom surface in direct contact with the bottom lamina layer. The top surface of the PCM layer and the bottom surface of the PCM layer can have a structurally stabilizing width ratio.