The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Feb. 20, 2023
Applicant:

Integrated Silicon Solution Inc., Milpitas, CA (US);

Inventors:

Kang Min Lee, Milpitas, CA (US);

Kwang Kyung Lee, Milpitas, CA (US);

Seung Cheol Bae, Milpitas, CA (US);

Young Jin Yoon, Milpitas, CA (US);

Sang Min Jun, Milpitas, CA (US);

Sun Byeong Yoon, Milpitas, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H01L 27/02 (2006.01); H03K 17/082 (2006.01);
U.S. Cl.
CPC ...
H02H 9/001 (2013.01); H01L 27/0288 (2013.01); H03K 17/0822 (2013.01);
Abstract

A semiconductor integrated circuit is provided, including: a first switch circuit; a logic circuit, coupled to the first switch circuit, a first floating diffusion point being defined between the first switch circuit and the logic circuit; a second switch circuit, coupled to the logic circuit, a second floating diffusion point being defined between the second switch circuit and the logic circuit; and a voltage holding circuit, coupled to the first floating diffusion point and the second floating diffusion point, and used to adjust the voltages of the floating diffusion points. The voltage holding circuit increases or decreases the voltage values of the first floating diffusion point and the second floating diffusion point. Thereby, the influence of long recovery time on the semiconductor integrated circuit is improved, and the stability is ensured.


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