The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Aug. 30, 2021
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Sylvain Barraud, Grenoble, FR;

Jean-Pierre Colinge, Grenoble, FR;

Bernard Previtali, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/8221 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 21/823885 (2013.01); H01L 27/0688 (2013.01); H01L 29/0673 (2013.01); H01L 29/1037 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); H01L 21/823828 (2013.01);
Abstract

A device with stacked transistors includes a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, and a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods. The source block of the second transistor is distinct from the source and drain block of the second transistor, and the drain block of the second transistor is distinct from the drain and source blocks of the second transistor.


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