The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Oct. 12, 2021
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Mark D. Kellam, Siler City, NC (US);

John Eric Linstadt, Palo Alto, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01);
Abstract

The embodiments are directed to technologies for variable pitch vertical interconnect design for scalable escape routing in semiconductor devices. One semiconductor device includes a circuit die, and an array of circuit die interconnects located on the circuit die. The array includes a first triangular octant of interconnects that are organized in rows and columns, each column incrementing its number of interconnects from a first side of the first triangular octant to a second side of the first triangular octant. A pitch size between the columns increases in a first repeating pattern from the first side to the second side.


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