The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Jan. 25, 2022
Applicant:

GE Aviation Systems Llc, Grand Rapids, MI (US);

Inventors:

Rinaldo Luigi Miorini, Niskayuna, NY (US);

Arun Virupaksha Gowda, Rexford, NY (US);

Naveenan Thiagarajan, Clifton Park, NY (US);

Brian Magann Rush, Niskayuna, NY (US);

Assignee:

GE AVIATION SYSTEMS LLC, Grand Rapids, MI (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/427 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4275 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/06 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/19 (2013.01); H01L 2224/214 (2013.01); H01L 2224/221 (2013.01); H01L 2224/24137 (2013.01);
Abstract

A power overlay (POL) module includes a semiconductor device having a body, including a first side and an opposing second side. A first contact pad defined on the semiconductor device first side and a dielectric layer, having a first side and an opposing second side defining a set of first apertures therethrough, is disposed facing the semiconductor device first side. The POL module, includes a metal interconnect layer, having a first side and an opposing second side, the metal interconnect layer second side is disposed on the dielectric layer first side) and extends through the set of first apertures to define a set of vias electrically coupled to the first contact pad. An enclosure defining an interior portion is coupled to the metal interconnect layer first side, and a phase change material (PCM) is disposed in the enclosure interior portion.


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