The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2025
Filed:
Jun. 29, 2022
Silicon Storage Technology, Inc., San Jose, CA (US);
Hieu Van Tran, San Jose, CA (US);
Thuan Vu, San Jose, CA (US);
Stanley Hong, San Jose, CA (US);
Stephen Trinh, San Jose, CA (US);
Anh Ly, San Jose, CA (US);
Han Tran, Ho Chi Minh, VN;
Kha Nguyen, Ho Chi Minh, VN;
Hien Pham, Ho Chi Minh, VN;
SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US);
Abstract
Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.