The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Supratim Pal, Folsom, CA (US);

Li-An Tang, El Dorado Hills, CA (US);

Changwon Rhee, Rocklin, CA (US);

Timothy R. Bauer, Hillsboro, OR (US);

Alexander Lyashevsky, Cupertino, CA (US);

Jiasheng Chen, El Dorado Hills, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/44 (2006.01); G06F 7/506 (2006.01); G06F 7/57 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 7/44 (2013.01); G06F 7/506 (2013.01); G06F 7/57 (2013.01); G06F 9/30112 (2013.01); G06F 9/30134 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/38885 (2023.08);
Abstract

An apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (MAD) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the MAD instruction to generate an output in a single clock cycle of the processor.


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