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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12236180 B1

PDFFull Text
Date of Patent:
Feb. 25, 2025

Filed:

Aug. 09, 2023

Integrated circuit and method of manufacturing the same

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Jung Chang, Hsinchu, TW;

Chin-Chang Hsu, Hsinchu, TW;

Hsien-Hsin Sean Lee, Duluth, GA (US);

Wen-Ju Yang, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Sonya McCall-Shepard

Int. Cl.
CPC ...
G06F 30/392 (2020.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 27/118 (2006.01); H01L 29/40 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); H01L 21/28008 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 27/0886 (2013.01); H01L 27/11807 (2013.01); H01L 29/401 (2013.01); H01L 29/4916 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01);
Abstract

A system for manufacturing an integrated circuit includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium. The processor is configured to execute the executable instructions for placing a set of gate layout patterns on a first layout level, and generating a cut feature layout pattern extending in the first direction. The set of gate layout patterns correspond to fabricating a set of gate structures of the integrated circuit. The cut feature layout pattern is on the first layout level, and overlap each of the layout patterns of the set of gate layout patterns at a same position in the second direction. The cut feature layout pattern identifies a location of a removed portion of a gate structure of the set of gate structures.

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