The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Dec. 21, 2022
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Aman Gupta, Sunnyvale, CA (US);

Krishnan Srinivasan, San Jose, CA (US);

Ahmad R. Ansari, San Jose, CA (US);

Sagheer Ahmad, Cupertino, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 12/1009 (2013.01); G06F 13/4036 (2013.01); G06F 13/4068 (2013.01); G06F 2213/0038 (2013.01);
Abstract

Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.


Find Patent Forward Citations

Loading…