IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12232435 B1

PDFFull Text
Date of Patent:
Feb. 18, 2025

Filed:

Apr. 03, 2023

Chip containing an onboard non-volatile memory comprising a phase-change material

Applicants:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Stmicroelectronics (Grenoble 2) Sas, Grenoble, FR;

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Franck Arnaud, St. Nazaire les Eymes, FR;

David Galpin, Le Cheylas, FR;

Stephane Zoll, Froges, FR;

Olivier Hinsinger, Barraux, FR;

Laurent Favennec, Villard Bonnot, FR;

Jean-Pierre Oddou, Saint-Ismier, FR;

Lucile Broussous, Goncelin, FR;

Philippe Boivin, Venelles, FR;

Olivier Weber, Grenoble, FR;

Philippe Brun, Meylan, FR;

Pierre Morin, Kessel-Lo, BE;

Assignees:

STMicroelectronics (Crolles 2) SAS, Crolles, FR;

STMicroelectronics (Grenoble 2) SAS, Grenoble, FR;

STMicroelectronics (Rousset) SAS, Rousset, FR;

Attorney:

Crowe & Dunlevy LLC

Primary Examiner:

Joshua Benitez Rosario

Assistant Examiner:

Christopher A Culbert

Int. Cl.
CPC ...
H10B 63/00 (2023.01); G11C 13/00 (2006.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10N 70/8616 (2023.02); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/011 (2023.02); H10N 70/021 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/8265 (2023.02); H10N 70/8413 (2023.02); H10N 70/882 (2023.02); G11C 2013/008 (2013.01);
Abstract

An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

Find Patent Forward Citations

Loading…