The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Dec. 31, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Yun Heub Song, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G11C 13/00 (2006.01); H01L 21/768 (2006.01); H01L 27/02 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10N 70/231 (2023.02); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H10B 12/50 (2023.02); H10N 70/841 (2023.02); H10B 12/01 (2023.02); H10N 70/883 (2023.02);
Abstract

Disclosed is a bi-directional two-terminal phase-change memory device using a tunneling thin film and a method of operating the same. According to an one embodiment, a phase-change memory device comprises: a first electrode; a second electrode; and a phase-change memory cell interposed between the first electrode and the second electrode, wherein the phase-change memory cell comprises: a P-type intermediate layer used as a data storage as a crystal state changes due to a voltage applied through the first electrode and the second electrode; an upper layer and a lower layer formed using an N-type semiconductor material at both ends of the intermediate layer; and at least one tunneling thin film disposed on at least one area from among an area between the upper layer and the intermediate layer or an area between the lower layer and the intermediate layer, so as to reduce a leakage current in the intermediate layer or prevent intermixing between a P-type dopant and an N-type dopant.


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