The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Aug. 18, 2022
Applicant:

Hefei Reliance Memory Limited, Hefei, CN;

Inventors:

Zhichao Lu, San Jose, CA (US);

Brent Steven Haukness, Monte Sereno, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/20 (2023.01); G11C 7/12 (2006.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10B 63/80 (2023.02); G11C 7/12 (2013.01); G11C 13/0007 (2013.01); G11C 13/003 (2013.01); H10B 63/82 (2023.02); H10N 70/021 (2023.02); H10N 70/063 (2023.02); H10N 70/24 (2023.02); H10N 70/801 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02); G11C 2213/52 (2013.01); G11C 2213/77 (2013.01);
Abstract

Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.


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