Memory device having 2-transistor vertical memory cell

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. The second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. The charge storage structure is located on a level of the apparatus between the first and second levels.