The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2025
Filed:
May. 13, 2022
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Yan Zhang, Westford, MA (US);
Johannes M. van Meer, Middleton, MA (US);
Sankuei Lin, Los Gatos, CA (US);
Baonian Guo, Andover, MA (US);
Naushad K. Variam, Marblehead, MA (US);
Assignee:
Applied Materials, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66553 (2013.01); H01L 29/78696 (2013.01);
Abstract
A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.