The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Jul. 31, 2020
Applicant:

Hitachi Energy Ltd, Zürich, CH;

Inventors:

Marco Bellini, Schlieren, CH;

Lars Knoll, Hägglingen, CH;

Assignee:

Hitachi Energy Ltd, Zürich, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/04 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1045 (2013.01); H01L 21/046 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7395 (2013.01); H01L 29/7802 (2013.01);
Abstract

A silicon carbide (SiC) planar transistor device includes a SiC semiconductor substrate of a first charge type, a SiC epitaxial layer of the first charge type formed at a top surface of the SiC semiconductor substrate, a source structure of the first charge type formed at a top surface of the SiC epitaxial layer, a drain structure of the first charge type formed at a bottom surface of the SiC semiconductor substrate, a gate structure comprising a gate runner and a gate dielectric that covers at least part of the source structure and the gate runner, and a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure. The channel can be formed by performing a plurality of implantation steps so that the channel region comprises a first region and a second region.


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