The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Dec. 21, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Sreenivasan K. Koduri, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 23/53204 (2013.01); H01L 24/03 (2013.01); H01L 2224/04042 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/10253 (2013.01);
Abstract

A method for interconnecting bond pads of semiconductor dies or devices with corresponding leads in a lead frame with printed conductive interconnects in lieu of bond wires and an apparatus resulting from the above method. More specifically, some examples include printing an insulating foundation path from bond-pads on a semiconductor die to leads of a lead frame to which the semiconductor die is attached. A foundation conductive trace is printed on top of the insulating foundation path from each bond pad on the die to a corresponding lead of the lead frame. Optionally, on top of the conductive trace, a cover insulating cover layer is applied on exposed portions of the conductive interconnects and the foundation insulating layer. Preferably, this can be the same material as foundation layer to fully adhere and blend into a monolithic structure, rather than separate layers. Optionally, a protective layer is then applied on the resulting apparatus.


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