The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Sep. 15, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

John S. Guzek, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/56 (2013.01); H01L 21/568 (2013.01); H01L 23/13 (2013.01); H01L 23/48 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 25/065 (2013.01); H01L 25/0657 (2013.01); H01L 25/07 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 2224/16 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2924/18161 (2013.01);
Abstract

Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.


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