The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2025
Filed:
Jun. 25, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Burak Baylav, Hillsboro, OR (US);
Dhananjay Bhawe, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); G06F 30/392 (2020.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); G06F 30/392 (2020.01); H01L 23/5222 (2013.01);
Abstract
An integrated circuit structure includes a plurality of interconnect lines and a plurality of dummy lines that are co-planar with the plurality of interconnect lines, where a ratio of line length to end-to-end spacing of the dummy lines varies inversely with a density of the interconnect lines within each of a plurality of regions. The regions are of approximately equal area within a rectangular grid array.
Baylav, Burak. (2025). Local density control for metal capacitance reduction (U.S. Patent No. 12230577). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12230577
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile