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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12230566 B1

PDFFull Text
Date of Patent:
Feb. 18, 2025

Filed:

Nov. 16, 2023

Metal-insulator-metal structure

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yuan-Yang Hsiao, Hsinchu, TW;

Hsiang-Ku Shen, Hsinchu, TW;

Dian-Hau Chen, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

HAYNES AND BOONE, LLP

Primary Examiner:

Patricia D Valenzuela

Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01); H01L 21/027 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/0214 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/76805 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 28/60 (2013.01); H01L 21/02164 (2013.01); H01L 21/02167 (2013.01); H01L 21/0217 (2013.01); H01L 21/02178 (2013.01); H01L 21/02189 (2013.01); H01L 21/0271 (2013.01); H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 28/40 (2013.01); H01L 28/87 (2013.01); H01L 29/94 (2013.01);
Abstract

Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.

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