The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Nov. 08, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Michael Apodaca, Folsom, CA (US);

Carsten Benthin, Voelklingen, DE;

Kai Xiao, San Jose, CA (US);

Carson Brownlee, Austin, TX (US);

Timothy Rowley, Austin, TX (US);

Joshua Barczak, Timonium, MD (US);

Travis Schluessler, Berthoud, CO (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/06 (2011.01); G06F 7/14 (2006.01); G06F 9/38 (2018.01); G06F 16/901 (2019.01); G06N 3/02 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 5/70 (2024.01);
U.S. Cl.
CPC ...
G06T 15/06 (2013.01); G06F 7/14 (2013.01); G06F 9/3877 (2013.01); G06F 16/9027 (2019.01); G06N 3/02 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 5/70 (2024.01); Y02D 10/00 (2018.01);
Abstract

Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.


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