The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12229489 B1

Date of Patent:

Feb. 18, 2025

Filed:

Nov. 21, 2023

System and method of verifying slanted layout components

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yuan-Te Hou, Hsinchu, TW;

Min-Yuan Tsai, Hsinchu County, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

FOLEY & LARDNER LLP

Primary Examiner:

Paul Dinh

Int. Cl.

CPC ...

G06F 30/39 (2020.01); G06F 30/31 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01);

U.S. Cl.

CPC ...

G06F 30/398 (2020.01); G06F 30/31 (2020.01); G06F 30/392 (2020.01);

Abstract

Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component. In one aspect, a slanted layout component having a side slanted from a base axis by an offset angle is detected. In one aspect, a first location of a vertex of the slanted layout component according to the offset angle is transformed to obtain a second location of a rotated vertex of a rotated layout component. In one aspect, layout verification is performed on the rotated layout component with respect to the base axis.

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