The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Aug. 16, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Fa-Long Luo, San Jose, CA (US);

Jaime Cummins, Bainbridge Island, WA (US);

Tamara Schmitz, Scotts Valley, CA (US);

Jeremy Chritz, Seattle, WA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/0864 (2016.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0207 (2013.01); G06F 12/0223 (2013.01); G06F 12/0292 (2013.01); G06F 12/0864 (2013.01); G06F 12/0893 (2013.01); G06F 12/06 (2013.01); G06F 2212/173 (2013.01); G06F 2212/206 (2013.01); G06F 2212/253 (2013.01);
Abstract

Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.


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